MOSFET scaling on bulk silicon has been the primary focus of the semiconductor and microelectronic industry for achieving CMOS chip performance and density objectives. The shrinking of MOSFET dimensions for high density, low power and enhanced performance requires reduced power-supply voltages. Because power consumption, P, is a function of capacitance, C, power supply voltage, V, and transition frequency, f, where P=CV.sup.2 f, the focus has been on reducing both C and V as the transition frequency increases. As a result, dielectric thickness and channel length are scaled with power-supply voltage. Power-supply reduction continues to be the trend for future low-voltage CMOS. However, with power supply reduction, transistor performance is severely impacted by both junction capacitance and the MOSFET body effect at lower voltages. As technologies scale below 0.25 .mu.m channel lengths, to 0.15- and 0.1 .mu.m. short-channel effects (SCE) control, gate resistance, channel profiling and other barriers become an issue for advanced CMOS technologies. While significant success has been achieved with successive scaling of bulk CMOS technology, the manufacturing control issues and power consumption will become more difficult to deal with.
Using silicon-on-insulator (SOI) substrates, many of the concerns and obstacles of bulk-silicon CMOS can be eliminated at lower power supply voltages. CMOS-on-SOI has significant advantages over bulk CMOS technology and will achieve the scaling objectives of low power and high performance for future technologies. CMOS-on-SOI provides low power consumption, low leakage current, low capacitance diode structures, good sub-threshold I-V characteristics (better than 60 mV/decade), a low soft error rate from both alpha particles and cosmic rays, good SRAM access times, and other technology benefits. SOI technology allows for the mapping of standard advanced technologies into an SOI technology without significant modifications. SOI process techniques include epitaxial lateral overgrowth (ELO), lateral solid-phase epitaxy (LSPE) and full isolation by porous oxidized silicon (FIPOS). SOI networks can be constructed using the semiconductor process of techniques of separation by implanted oxygen (SIMOX) and wafer-bonding and etch-back (SIBOND) because they achieve low defect density, thin film control, good minority carrier lifetimes and good channel mobility characteristics. Structural features are defined by shallow-trench isolation (STI). Shallow-trench isolation eliminates planarity concerns and multidimensional oxidation effects, such as LOCOS bird's beak, thereby allowing technology migration and scaling to sub-0.25 .mu.m technologies.
There are multiple concerns in SOI technology. Thermal dissipation of the electrical-current generated self heating is a concern. In this case, the ability to establish a low-thermal resistance contact to the bulk (e.g., thermal contacts) can reduce this concern.
In thin-film SOI technology, there are no vertical diodes, vertical transistors, vertical pnpn or other bulk type elements normally used for analog applications. Analog circuit and device elements that can be placed in the bulk silicon can be used to reduce chip area and achieve bulk-silicon like circuit operation.
Another barrier is electrostatic discharge protection (ESD). One problem with SOI is that there are no diodes natural to the process that are not in the presence of a polysilicon gate edge. In thin-film SOI technology, there are no vertical diodes, vertical transistors, vertical pnpn or other bulk type elements normally used for electrostatic discharge protection. ESD circuit and device elements that can be placed in the bulk silicon can be used to reduce chip area and achieve bulk-silicon like circuit operation. To achieve ESD robustness in a mainstream SOI technology suitable for high volume commercial usage, ESD protection structures and circuitry must have low resistance and capacitance as well as a small percentage of semiconductor chip area. The disadvantage of SOI ESD networks is 1) high thermal impedance to the bulk substrate, 2) thin films, 3) polysilicon gate structures, and 4) the lack of vertical silicon diodes. The high-thermal impedance creates high surface temperatures in the SOI film leading to thermal secondary breakdown in SOI devices. The thin film SOI devices leads to high current densities creating significant power/density constraints. The polysilicon gate structures create high capacitance and are prone to electrical overload and dielectric breakdown. The lack of vertical structures prevents electrical current to be dissipated to the bulk and forces construction of wide perimeter lateral structures. As a result, a disadvantage for SOI is that negative pulse ESD protection is as difficult as the positive pulse ESD protection. In bulk silicon, using comparatively smaller structures, ESD protection for negative mode pulses is easily achieved because of current dissipation to the bulk substrate; in SOI this is not true. This forces designers to allocate as much area for negative mode as the positive mode protection schemes.
In the prior art, there are different alternatives suggested to date to achieve ESD protection. Standard circuits are constructed in SOI and used for ESD protection. K. Verhaege et al. ("Analysis of Snapback in SOI NMOSFETs and its Use for an SOI ESD Protection Circuit," Proceedings of the IEEE SOI Conference, pp. 140-141, 1992), and ("Double Snapback in SOI NMOSFETs and its Application for SOI ESD Protection." IEEE Electron Device Lett., Vol. 14, No. 7, July 1993, pp. 326-328) demonstrates that usage of a SOI MOSFET transistor as an ESD protection device. Lu (U.S. Pat. No. 4,989,057, ESD Protection for SOI Circuits) demonstrates the usage of transistors in the SOI film for ESD protection. Voldman et al. ("CMOS-on-SOI ESD Protection Networks," EOS/ESD Proceedings, September 1996) demonstrates that thin film SOI ESD devices can be constructed by configuring MOSFETs in diode modes of operation. The First problem is that SOI-based ESD circuits are worse than bulk devices by at least a factor of 2.times.. M. Chan et al. ("Comparison of ESD Protection Capability of SOI and Bulk CMOS Output Buffers," IRPS 1994) have demonstrated that SOI circuits are 2.times. less ESD robust. This then will require very large ESD networks which will be unacceptable in size or capacitance loading. A second problem is that the structures are all MOSFET based. All of the above structures introduce a polysilicon gate structure. The concern with the polysilicon gate structure is dielectric overload and high capacitance per unit width. Both of these solutions are unacceptable from a reliability and functional perspective.
In the implementations, the structures utilize only bulk elements adjacent to the active core SOI circuitry. Kawai, U.S. Pat. No. 4,889,829, demonstrates a method of building bulk transistors in the substrate and SOI transistors in the insulating film. In this methodology, it is required that the bulk transistor be constructed adjacent to the active area structures in the same plane. This requires additional chip area devotee to the bulk transistors as well as Topography concerns. Kawai introduces significant topography. which would make it unacceptable for high density and planarity integration issues.
Sun, U.S. Pat. No. 5,399,507, proposed a mixed thin film where ESD devices are constructed in the bulk and where the oxygen implant is masked and core SOI devices are built over the insulating layer. In the concept, the ESD MOSFET structures are placed adjacent to the active integrated circuits in the same physical silicon plane. This concept eliminates planarity concerns but leads to silicon dislocation, which are unacceptable from a manufacturing perspective. To avoid the silicon dislocations, the active core SOI structures must be spatially separated to avoid yield concerns. This introduces an area disadvantage. Whereas the proposed solutions solve the concern of building ESD networks in the thin SOI film, they do not resolve semiconductor manufacturing problems, yield issues and topography.
In the above, no ESD solution has been proposed that uses ESD structures under active circuitry to eliminate the problem of semiconductor chip area. In Kawai and Sun, the use of SOI MOSFETs and diode structures for ESD devices is avoided by constructing bulk MOSFET devices. In Verheage and Lu, bulk devices are avoided. Hence in the prior art, there is no obvious incentive to use both bulk and SOI transistors for ESD protection. Also, three-dimensional structures have not been suggested or proposed as ESD solutions. This is because it is not possible to build bulk MOSFETs under SOI MOSFETs. Using a dual-gate MOSFET, Ohmi, U.S. Pat. No. 4,907,053, addresses the problem of back gate biasing in a SOI MOSFET transistor. Ohmi suggests the possibility of constructing a SOI MOSFET with a top gate and a bottom gate where the bottom gate is placed in the bulk and the top gate is above the SOI film. The implementation suggested by Ohmi interconnection is not addressed in the structure.
Structural elements that need to be interconnected are the MOSFET top gate, bottom gate, body, and source/drain diffusions and bulk structural elements.
SOI structures can contain a top gate and bottom gate structure. In SIBOND implementations, a buried bottom gate can exist within the buried oxide layer. In a SIMOX implementation, a diffused second gate can be present and formed in the silicon substrate. Interconnect structures arc needed to establish electrical connections between the silicon surface, the body, bottom gate, and bulk device elements. Interconnect elements between the different elements can be advantageous for single gale CMOS-on-SOI, dual gate CMOS-on-SOI, dynamic threshold MOSFETs (DTMOS). In dynamic threshold MOSFETs, the body of the MOSFET is used to dynamically vary the threshold voltage of the MOSFET transistor.
An issue of SOI is the "body contact." A concern is the additional areas needed for establishing an electrical connection between the body and an electrical potential. In bulk CMOS, the substrate acts as the natural plane for the "MOSFET body." In SOI, new three dimensional structures are advantageous for establishing connections between the body and power supply connections, bulk devices or bulk contacts.
An advantage in dual-gate CMOS-on-SOI, interconnects to connect either a buried gate or a diffused bulk gate can be advantageous to avoid additional silicon area.
In dynamic threshold MOSFETs, interconnects to connect either a buried gate or a diffused bulk gate to the MOSFET body can be advantageous to reduce additional silicon area.
For three dimensional circuits, that consist of either bulk elements, or both bulk, and SOI elements, interconnections between these elements are needed to reduce additional silicon area.
For bulk ESD networks, that consist of either bulk elements, or both bulk and SOI elements, interconnections between these elements are needed to reduce additional silicon area